1. Field of the Invention
The present invention relates to a line for transmitting a high-frequency signal in an electronic device.
2. Discussion of the Related Art
The transmission of a signal of high frequency, typically greater than 300 MHz, from one point to another of an electronic device, for example, from one point to another of an integrated circuit chip, requires the use of specific propagation lines, or waveguides. Two types of transmission lines are mainly used, microstrips and coplanar lines.
A microstrip comprises a conductive track superposed to a ground plane made of a conductive material and separated therefrom by a dielectric layer.
A coplanar line comprises, in the same plane, a conductive track surrounded with two conductive ground planes and separated therefrom by a dielectric material. Transmission lines of microstrip type are more specifically considered herein.
FIG. 1 is a cross-section view schematically showing a microstrip formed in the upper portion of a semiconductor chip 1 (the cross-sectional plane is orthogonal to the signal propagation direction).
Chip 1 is formed inside and on top of a semiconductor substrate 3, for example a silicon substrate. The upper surface of substrate 3 is coated with a stack 5 of metallic and insulating layers, where various chip component interconnects (not shown in the drawing) may especially be formed. In this example, stack 5 comprises six different metallization levels M1 to M6, M1 and M6 respectively being the level closest to the substrate (lower level) and the level most remote from the substrate (upper level). The insulating layers of the stack are, for example, made of silicon oxide.
The shown transmission line comprises a ground plane 7, formed in lower metallization level M1 . As a variation, ground plane 7 may also be formed in several lower metallization levels, for example, levels M1 and M2.
The transmission line further comprises, above the ground plane, a conductive track or strip 8 of width W smaller than the width of ground plane 7. Strip 8 is formed in upper metallization level M6. No intermediary metallization is formed between ground plane 7 and strip 8, so that strip 8 is only separated from ground plane 7 by a dielectric layer 9 of thickness e, where e is the distance between levels M2 and M6.
When a high-frequency signal is applied on conductive strip 8, it propagates in the transmission line.
Characteristic impedance ZC of the line should be specifically matched to the impedance of the components connected to the input and to the line output. A poorly matched impedance would cause losses by reflection of the signal on the load impedance.
Considering a line with no loss, characteristic impedance ZC of the line especially depends on capacitance C formed between strip 8 and ground plane 7, and on inductance L formed by strip 8, according to relation ZC=√{square root over (L/C)}.
In practice, linear attenuation coefficient a of the line is defined by relation α=R/(2*ZC), where R designates the resistance per unit length of the line.
Thus, to minimize the linear attenuation of the line, one should both limit the resistive loss and maintain a high characteristic impedance.
In practice, for a given manufacturing technology, the thicknesses of the conductive and insulating materials of stack 5 are difficult to modify. Thus, only the selection of width W of strip 8 and of the metallization levels used to form strip 8 and ground plane 7 enable to optimize impedance ZC. The selection of the metallization levels especially determines thickness e of dielectric layer 9, which conditions capacitance C.
Width W of strip 8 is generally desired to be as high as possible to limit the resistive loss introduced by the line. This, however, results in increasing capacitance C and thus in decreasing impedance ZC of the line. For an aimed impedance ZC, to have as wide a strip 8 as possible, it is generally chosen, as illustrated in FIG. 1, to form strip 8 and ground plane 7 in the end metallization levels of the chip (respectively in the most remote level(s) and in the closest level(s) with respect to the substrate). This enables to maximize thickness e of dielectric layer 9, to decrease capacitance C, and thus to maintain a relatively high characteristic impedance.
The attenuation introduced by the line however remains significant. In silicon technology, to form integrated circuits capable of processing signals of millimetric wavelengths, the maximum available thickness between the end metallization levels of the chip (strip 8 and ground plane 7) can reach 10 μm. To reach a 50-ohm impedance ZC, width W of strip 8 must be smaller than 10 μm. This results in a strong attenuation of the signal running through the line, for example, a 0.5-dB/mm attenuation at 60 GHz. This attenuation is mainly due to the resistive loss increased by the narrowness of strip 8.
It would be desirable to have high-frequency transmission lines having a lower linear attenuation.
The transmission of high-frequency signals in chip stacking devices is more specifically considered herein.